ODE4EC-DIG

ODE4EC-DIG aims to develop a complete, open-source Electronic Design Automation (EDA) flow for digital System-on-Chip (SoC) design, targeting advanced 65-28nm technology nodes. This project addresses Europe's dependency on costly, foreign EDA tools by creating accessible alternatives for research and SMEs, and reducing costs for industrial design flows. The primary objective is to deliver an integrated high-level to GDSII design flow, enabling automated ASIC generation from C/C++ to physical layout. To achieve this goal, the project will improve the quality, stability, and reliability of the core EDA tools. It will provide more accurate timing models and dynamic power estimations. Tool interoperability and flow orchestration will be improved through standardized APIs, which will also ensure sustainable and reproducible design flows. Machine learning will automate multi-objective optimization to improve PPA (Power, Performance, and Area) metrics. Memory integration will be streamlined by developing a standard interface and validated SRAM macros. The project will also support advanced packaging and die-to-die communication with open Application Design Kits (ADKs) and physical demonstrators. The tools will be validated through rigorous testing and multiple tapeouts. The consortium is built on a strong and active community of developers and strives to involve more users who can contribute to developing and maintaining open-source EDA tools. By facilitating knowledge sharing and collaboration, ODE4EC-DIG aims to accelerate the adoption of open-source EDA solutions and drive the growth of the European microelectronics ecosystem. ODE4EC-DIG addresses the "Open-source EDA tools development" call, aiming to improve and deliver open-source EDA tools for large-scale designs. It focuses on parasitic extraction, memory generators, hierarchical flows, timing and power analysis, and SoC integration, aligning with the Chips JU Multi Annual Work programme 2023-2027.